M68AW512D
Figure 7. Address Controlled, Read Mode AC Waveforms
A0-A18
tAVQV
tAVAV
VALID
tAXQX
DQ0-DQ7 and/or DQ8-DQ15
DATA VALID
Note: E1 = Low, E2 = High, G = Low, W = High, UB = Low and/or LB = Low.
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
AI05839
A0-A18
E1
tAVQV
tELQV
tAVAV
VALID
tAXQX
tEHQZ
E2
G
DQ0-DQ15
UB, LB
Note: Write Enable (W) = High
tELQX
tGLQV
tGLQX
tBLQV
tBLQX
tGHQZ
VALID
tBHQZ
AI05981b
12/22