M68AW512 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M68AW512

8 Mbit (512K x16) 3.0V Asynchronous SRAM

STMicroelectronics 

M68AW512D

Figure 13. E1 Controlled, Low VCC Data Retention AC Waveforms

3.6V

VCC

2.7V

VDR > 1.5V

E1 or UB/LB

DATA RETENTION MODE

tCDR

E1 ≥ VDR – 0.2V or UB = LB ≥ VDR – 0.2V

tR

AI05985

Figure 14. E2 Controlled, Low VCC Data Retention AC Waveforms

3.6V

VCC

2.7V

VDR > 1.5V

E2

DATA RETENTION MODE

tCDR

E2 < 0.2V

tR

AI05986c

Table 9. Low VCC Data Retention Characteristics

Symbol

Parameter

Test Condition

Min

ICCDR (1) Supply Current (Data Retention)

VCC = 1.5V, E1 ≥ VCC –0.2V or

E2 ≤0.2V or UB = LB ≥ VCC –0.2V, f = 0

tCDR (1,2)

Chip Deselected to Data

Retention Time

0

tR (2) Operation Recovery Time

tAVAV

VDR (1) Supply Voltage (Data Retention)

E1 ≥ VCC –0.2V or E2 ≤0.2V or

UB = LB ≥ VCC –0.2V, f = 0

1.5

Note: 1. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤0.2V.

2. Tested initially and after any design or process that may affect these parameters. tAVAV is Read cycle time.

3. No input may exceed VCC +0.2V.

Max

30

Unit

µA

ns

ns

V

18/22

Share Link: