MB90660A Series
(2) Block Diagrams
• Timer/wave generator block diagram
TRG
(External Input)
CLRR, CLRBR
Reverse
or Clear Comparator
14-bit Timer
STCR, TMST, MODE
CES1, 0
TCS1, 0
Count Clock Pre-scalar
(1, 2, 8 or 16 machine cycles)
Zero detect
Zero detect interrupt mask
ZOSC, IME, CYC3 to 0
Interrupt Control
IIOS
TCIE, TCIR
TZIE, TZIR
TMIE, TMIR
CIE3 to 0, CIR3 to 0
Timer Clear
Zero detect interrupt
Timer interrupt
Compare interrupt
14
Zero detect
Zero detect pin control Set, Reset
ZSB0
Set, Reset,
Comparator, pin control Transfer
RO01, 0
PDR6
PD66
OCPR0, OCPBR0
RT0
(External Output)
Zero detect pin control Set, Reset
ZSB1
Set, Reset,
Comparator, pin control Transfer
RO11, 0
PDR6
PD60
OCPR1, OCPBR1
RT1
(to Output Selector)
Zero detect pin control Set, Reset
ZSB2
Set, Reset,
Comparator, pin control Transfer
RO21, 0
PDR6
PD61
OCPR2, OCPBR2
RT2
(to Output Selector)
Transfer request
Buffer transfer control
TREN, TMSK, BFS1, 0
Zero detect pin control Set, Reset
ZSB3
Set, Reset,
Comparator, pin control Transfer
RO31, 0
PDR6
PD62
OCPR3, OCPBR3
RT3
(to Output Selector)
31