MB90P663APFM View Datasheet(PDF) - Fujitsu

Part Name

Description

Manufacturer

MB90P663APFM

16-bit Proprietary Microcontroller

Fujitsu 

MB90660A Series

8. Delayed Interrupt Generation Module

The delayed interrupt generation module is used to generate an interrupt for task switching. If this module is

used, an interrupt request to the F2MC-16L CPU can be generated or cancelled by software.

(1) Register Configuration

Delayed interrupt request

generation/cancel register

Address : 000009H

bit 15 14 13 12 11 10

–

–

–

–

–

–

98

– R0

DIRR

Read/Write

Initial value

(–) (–) (–) (–) (–) (–) (–) (R/W)

(–) (–) (–) (–) (–) (–) (–) (0)

The DIRR register controls the generation and cancellation of delayed interrupt requests. A delayed interrupt

request is generated when “1” is written to this register, while a delayed interrupt request is cancelled when “0”

is written here. Request cancel status results upon reset. Although either “0” or “1” may be written into reserved

bits, we recommend using the set bit and clear bit instructions when accessing this register in consideration of

possible future extensions.

(2) Block Diagram

Delayed interrupt source generation/

cancel decoder

Source latch

41

Share Link: