MB90P663APFM View Datasheet(PDF) - Fujitsu

Part Name

Description

Manufacturer

MB90P663APFM

16-bit Proprietary Microcontroller

Fujitsu 

MB90660A Series

9. Watchdog Timer and Timebase Timer Functions

The watchdog timer consists of a 2-bit watchdog counter using carry signals from the 18-bit timebase timer as

the clock source, a control register, and a watchdog reset controller.

In addition to an 18-bit timer, the timebase timer consists of a circuit for controlling interval interrupts. Note that

the timebase timer uses the main clock regardless of the status of the MCS bit within the CKSCR register.

(1) Register Configuration

Watchdog timer

bit 7

6

5

4

3

2

1

0

control register

Address : 0000A8H

PONR – WRST ERST SRST WTE WT1 WT0

Read/Write

(R) (–) (R) (R) (R) (W) (W) (W)

Initial value

(X) (–) (X) (X) (X) (1) (1) (1)

Timebase timer

bit 15 14

control register

Address : 0000A9H

Reserved –

Read/Write

(–) (–)

Initial value

(1) (–)

13 12 11 10 9 8

– TBIE TBOF TBR TBC1 TBC0

(–) (R/W) (R/W) (W) (R/W) (R/W)

(–) (0) (0) (1) (0) (0)

WDTC

TBTC

(2) Block Diagram

TBTC

TBC1

TBC0

TBR

TBIE

TBOF

Selector

AND

S

QR

212

214

216

219

TBTRES

Clock input

22

Timebase timer

29

212 214 216 219

Main clock

(OSC oscillation)

to PWM timer

Timebase

interrupt

WDTC

WT1

WT0

WTE

Selector

2-bit counter

OF

CLR

Watchdog reset

generator

CLR

to WDGRST

internal reset

generator

PONR

WRST

ERST

SRST

42

from power-on generator

RST pin

from RST bit of

STBYC register

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