MB90660A Series
(5) UART timing
Parameter
Serial clock cycle time
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
SCK ↑ → valid SIN hold
time
Serial clock
H pulse width
Serial clock
L pulse width
SCK ↓ → SOT delay time
Valid SIN → SCK ↑
SCK ↑ → valid SIN hold
time
Symbol
Pin
name
tSCYC SCK
tSLOV
SCK
SOT
tIVSH
SCK
SIN
tSHIX
SCK
SIN
(VCC = +2.7 V to +5.5 V, VSS = 0.0 V, TA = –40°C to +85°C)
Conditions
Value
Unit
Min. Max.
Remarks
—
8 tCP
—
ns
VCC = 5.0 V ±10% –80 80
ns
VCC = 3.0 V ±10% –120 120
VCC = 5.0 V ±10% 100
—
VCC = 3.0 V ±10% 200
—
ns CL = 80 pF + 1 TTL
ns
for internal clock
operation output
ns pin
VCC = 5.0 V ±10% 60
—
ns
VCC = 3.0 V ±10% 120
—
ns
tSHSL SCK
—
4 tCP
—
ns
tSLSH SCK
tSLOV
tIVSH
tSHIX
SCK
SOT
SCK
SIN
SCK
SIN
—
4 tCP
—
VCC = 5.0 V ±10% —
150
VCC = 3.0 V ±10% —
200
VCC = 5.0 V ±10% 60
—
VCC = 3.0 V ±10% 120
—
VCC = 5.0 V ±10% 60
—
VCC = 3.0 V ±10% 120
—
ns
ns CL = 80 pF + 1 TTL
for external clock
ns operation output
ns pin
ns
ns
ns
Notes: • These are AC specification during CLK synchronous mode.
• CL is the load capacity value assigned to the pin during testing.
• tCP is the machine cycle time (unit: ns).
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