MCF51QM32VFM(2012) View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MCF51QM32VFM
(Rev.:2012)

Embedded - Microcontrollers, Integrated Circuits (ICs)

Freescale Semiconductor 

Num

EP6

EP7

EP8

EP9

Memories and memory interfaces

Table 21. EzPort switching specifications (continued)

Description

EZP_CK high to EZP_D input invalid (hold)

EZP_CK low to EZP_Q output valid (setup)

EZP_CK low to EZP_Q output invalid (hold)

EZP_CS negation to EZP_Q tri-state

Min.

Max.

Unit

0.0

—

ns

—

25

ns

0.0

—

ns

—

12

ns

EZP_CK

EZP_CS

EZP_Q (output)

EZP_D (input)

EP3

EP4

EP2

EP9

EP8

EP7

EP5

EP6

Figure 6. EzPort Timing Diagram

6.4.3 Mini-Flexbus Switching Specifications

All processor bus timings are synchronous; input setup/hold and output delay are given in

respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be

the same as the internal system bus frequency or an integer divider of that frequency.

The following timing numbers indicate when data is latched or driven onto the external

bus, relative to the Mini-Flexbus output clock (FB_CLK). All other timing relationships

can be derived from these values.

Table 22. Flexbus switching specifications

Num

FB1

Description

Operating voltage

Frequency of operation

Clock period

Min.

1.71

—

40

Max.

3.6

25

—

Unit

V

MHz

ns

Notes

Table continues on the next page...

MCF51QM128 Data Sheet, Rev. 6, 01/2012.

Freescale Semiconductor, Inc.

33

Share Link: