MCP25050-E/SL View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
MCP25050-E/SL Datasheet PDF : 66 Pages
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MCP2502X/5X
REGISTER 7-9:
A/D OM RESULT REGISTER (AN10L)
R-x
R-x
U-x
U-x
AN1R.1 AN1R.0
—
—
bit 7
R-x
R-x
U-x
AN0R.1 AN0R.0
—
U-x
—
bit 0
bit 7-6
bit 5-4
bit 3-2
bit 1-0
AN1R.1:AN1R.0: A/D Channel 1, bits 1:0 results
Unimplemented: Reads as ‘0’
AN0R.1:AN0R.0: A/D Channel 0, bits 1:0 results
Unimplemented: Reads as ‘0’
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
TABLE 7-2: REGISTERS ASSOCIATED WITH THE A/D MODULE
Addr
1Eh
34h
00h
01h
0Eh
0Fh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
10h
Name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Value on
POR
Value on
RST
GPPIN
GP7
GP6
GP5
GP4
GP3
GP2
GP1
GP0 0000 0000 0000 0000
GPDDR * —
DDR6
DDR5
DDR4
DDR3
DDR2
DDR1
DDR0 -111 1111 -111 1111
IOINTEN GP7TXC GP6TXC GP5TXC GP4TXC GP3TXC GP2TXC GP1TXC GP0TXC 0000 0000 0000 0000
IOINTPO GP7POL GP6POL GP5POL GP4POL GP3POL GP2POL GP1POL GP0POL 0000 0000 0000 0000
ADCON0 ADON T0PS2
T0PS1
T0PS0 GO/DONE
—
CHS1
CHS0 0000 0-00 0000 0-00
ADCON1 ADCS1 ADCS0 VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 0000 0000 0000 0000
ADCMP3 AN3CM AN3CMP. AN3CMP. AN3CMP. AN3CMP.5 AN3CMP.4 AN3CMP. AN3CMP2 xxxx xxxx uuuu uuuu
ADCMP3 AN3CM AN3CMP.
—
—
Reserved
ADPOL xx-- ---- uu-- ----
ADCMP2 AN2CM AN2CMP. AN2CMP. AN2CMP. AN2CMP.5 AN2CMP.4 AN2CMP. AN2CMP2 xxxx xxxx uuuu uuuu
ADCMP2 AN2CM AN2CMP.
—
—
Reserved
ADPOL xx-- ---- uu-- ----
ADCMP1 AN1CM AN1CMP. AN1CMP. AN1CMP. AN1CMP.5 AN1CMP.4 AN1CMP. AN1CMP2 xxxx xxxx uuuu uuuu
ADCMP1 AN1CM AN1CMP.
—
—
Reserved
ADPOL xx-- ---- uu-- ----
ADCMP0 AN0CM AN0CMP. AN0CMP. AN0CMP. AN0CMP.5 AN0CMP.4 AN0CMP. AN0CMP2 xxxx xxxx uuuu uuuu
ADCMP0 AN0CM AN0CMP.
—
—
Reserved
—
xx-- ---- uu-- ----
STCON STEM STMS
STBF1
STBF0
STM3
STM2
STM1
STM0 0xxx xxxx 0uuu uuuu
* The GPDDR register controls the direction of the GPIO pins, even when they are being used as analog inputs. The user must ensure
that the bits in the GPDDR register are maintained set (input) when using them as analog inputs.
DS21664D-page 46
© 2007 Microchip Technology Inc.
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