MSC7119VM1200 View Datasheet(PDF) - Freescale Semiconductor

Part Name

Description

Manufacturer

MSC7119VM1200

Low-Cost 16-bit DSP with DDR Controller and 10/100 Mbps Ethernet MAC

Freescale Semiconductor 

Electrical Characteristics

2.5.3.2 Reset Configuration

The MSC7119 has two mechanisms for writing the reset configuration:

• From a host through the host interface (HDI16)

• From memory through the I2C interface

Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and

operating conditions:

• BM[0–1]

• SWTE

• H8BIT

• HDSP

2.5.3.3 Reset Timing Tables

Table 16 and Figure 4 describe the reset timing for a reset configuration write.

Table 16. Timing for a Reset Configuration Write

No.

Characteristics

1

2

Note:

Required external PORESET duration minimum

Delay from PORESET deassertion to HRESET deassertion

Timings are not tested, but are guaranteed by design.

Expression

16/FCLKIN

521/FCLKIN

Unit

clocks

clocks

PORESET

Input

PORESET

Internal

HRESET

Output(I/O)

1

Configuration Pins

are sampled

2

Figure 4. Timing Diagram for a Reset Configuration Write

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

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