M48T08-100PC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

M48T08-100PC

CMOS 8K x 8 TIMEKEEPER SRAM

STMicroelectronics 

Figure 3. Block Diagram

OSCI

OSCO

FT/OUT

VCC

VSS

VBAT

OSCILLATOR

32.768 kHz

POWER ON

RESET

SCL

SDA

SERIAL

BUS

INTERFACE

MK41T56

DIVIDER

CONTROL

LOGIC

1 Hz

SECONDS

MINUTES

HOURS

DAY

DATE

MONTH

YEAR

CONTROL

ADDRESS

REGISTER

RAM

(56 x 8)

AI00586B

DESCRIPTION (cont’d)

Typical data retention time is in excess of 10 years

with a 39 mA/h 3V lithium cell. The MK41T56 clock

is supplied in 8 Pin Plastic Dual-in-Line and 8 pin

Plastic Small Outline packages.

OPERATION

The MK41T56 clock operates as a slave device on

the serial bus. Access is obtained by implementing

a start condition followed by the correct address

(D0). The 64 bytes contained in the device can then

be accessed sequentially in the following order:

1.

Seconds Register

2.

Minutes Register

3.

Hours Register

4.

Day Register

5.

Date Register

6.

Month Register

7.

Years Register

8.

Control Register

9 to 64. RAM

AC MEASUREMENT CONDITIONS

Input Rise and Fall Times

Input Pulse Voltages

Input and Output Timing Ref. Voltages

≤ 5ns

0 to 3V

1.5V

Note that Output Hi-Z is defined as the point where data

is no longer driven.

Figure 4. AC Testing Load Circuit

5V

DEVICE

UNDER

TEST

1kΩ

1.8kΩ

OUT

CL = 100pF

CL includes JIG capacitance

AI01019

3/14

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