M48T08-100PC View Datasheet(PDF) - STMicroelectronics
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Description
Manufacturer
M48T08-100PC Datasheet PDF : 73 Pages
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MK41T56
Table 9. AC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 4.5V to 5.5V)
Symbol
Parameter
Min
Max
Unit
fSCL
SCL Clock Frequency
0
100
kHz
tLOW
Clock Low Period
4.7
µs
tHIGH
Clock High Period
4
µs
tR
SDA and SCL Rise Time
1
µs
tF
SDA and SCL Fall Time
300
ns
tHD:STA
START Condition Hold Time
(after this period the first clock pulse is generated)
4
µs
tSU:STA
tSU:DAT (1)
tHD:DAT
START Condition Setup Time
(only relevant for a repeated start condition)
Data Setup Time
Data Hold Time
4.7
µs
250
ns
0
µs
tSU:STO STOP Condition Setup Time
4.7
µs
tBUF
Time the bus must be free before a new transmission can start
4.7
µs
tI
Noise suppresion time constant at SCL and SDA input
0.25
1
µs
Note: 1. Transmitter must internally provide a hold time to bridge the undefined region (300ns max.) of the falling edge of SCL.
2-WIRE BUS CHARACTERISTICS (cont’d)
Accordingly, the following bus conditions have
been defined:
Bus not busy. Both data and clock lines remain
High.
Start data transfer. A change in the state of the
data line, from High to Low, while the clock is High,
defines the START condition.
Stop data transfer. A change in the state of the
data line, from Low to High, while the clock is High,
defines the STOP condition.
Data valid. The state of the data line represents
valid data when after a start condition, the data line
is stable for the duration of the High period of the
clock signal. The data on the line may be changed
during the Low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a start condition
and terminated with a stop condition. The number
of data bytes transferred between the start and stop
conditions is not limited. The information is trans-
mitted byte-wide and each receiver acknowledges
with a nineth bit.
Within the bus specifications a low speed mode
(2kHz clock rate) and a high speed mode (100kHz
clock rate) are defined. The MK41T56 clock works
in both modes. By definition a device that gives out
a message is called ”transmitter”, the receiving
device that gets the message is called ”receiver”.
The device that controls the message is called
”master”. The devices that are controlled by the
master are called ”slaves”.
Acknowledge. Each byte of eight bits is followed
by one acknowledge bit. This acknowledge bit is a
low level put on the bus by the receiver whereas
the master generates an extra acknowledge re-
lated clock pulse.
A slave receiver which is addressed is obliged to
generate an acknowledge after the reception of
each byte. Also a master receiver must generatean
acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is a stable Low during
the High period of the acknowledge related clock
pulse. Of course, setup and hold times must be
taken into account. A master receiver must signal
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