NAND256R4A2BZB6T View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
NAND256R4A2BZB6T
STMicroelectronics
NAND256R4A2BZB6T Datasheet PDF : 57 Pages
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
Table 21. AC Characteristics for Operations
Symbol
Alt.
Symbol
Parameter
1.8V
Devices
3V
Devices
Unit
tALLRL1
tALLRL2
tAR
Address Latch Low to Read Electronic Signature
Read Enable Low
Read cycle
Min
10
Min
10
10
ns
10
ns
tBHRL
tRR Ready/Busy High to Read Enable Low
Min
20
20
ns
tBLBH1
Read Busy time, 128Mb, 256Mb,
512Mb Dual Die
Max
12
tBLBH2
Ready/Busy Low to
tPROG Ready/Busy High
Read Busy time, 512Mb, 1Gb
Program Busy time
Max
15
Max 500
12
µs
12
µs
500 µs
tBLBH3
tBERS
Erase Busy time
Max
3
3
ms
tBLBH4
Reset Busy time, during ready
Max
5
5
µs
Reset Busy time, during read
Max
5
tWHBH1
tRST
Write Enable High to
Ready/Busy High
Reset Busy time, during program
Max
10
Reset Busy time, during erase
Max 500
5
µs
10
µs
500 µs
tCLLRL
tCLR Command Latch Low to Read Enable Low
Min
10
10
ns
tDZRL
tIR Data Hi-Z to Read Enable Low
Min
0
0
ns
tEHBH
tCRY Chip Enable High to Ready/Busy High (E intercepted read) Max 60 + tr(1) 60 + tr(1) ns
tEHEL
tCEH Chip Enable High to Chip Enable Low(2)
Min 100
100 ns
tEHQZ
tCHZ Chip Enable High to Output Hi-Z
Max
20
20
ns
tELQV
tCEA Chip Enable Low to Output Valid
Max
45
45
ns
tRHBL
tRB Read Enable High to Ready/Busy Low
Max 100
100 ns
tRHRL
tREH
Read Enable High to
Read Enable Low
Read Enable High Hold time
Min
15
15
ns
tRHQZ
tRHZ Read Enable High to Output Hi-Z
Min
15
Max
30
15
ns
30
tRLRH
tRP
Read Enable Low to
Read Enable High
Read Enable Pulse Width
Min
30
30
ns
tRLRL
tRC
Read Enable Low to
Read Enable Low
Read Cycle time
Min
60
50
ns
tRLQV
tREA
Read Enable Low to
Output Valid
Read Enable Access time
Read ES Access time(3)
Max
35
35
ns
tWHBH
Read Busy time, 128Mb, 256Mb,
tR
Write Enable High to 512Mb Dual Die
Ready/Busy High
Max
12
Read Busy time, 512Mb, 1Gb
Max
15
12
µs
12
µs
tWHBL
tWB Write Enable High to Ready/Busy Low
Max 100
100 ns
tWHRL tWHR Write Enable High to Read Enable Low
Min
80
60
ns
tWLWL
tWC
Write Enable Low to
Write Enable Low
Write Cycle time
Min
60
50
ns
Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures 34, 35 and 36.
2. To break the sequential read cycle, E must be held High for longer than tEHEL.
3. ES = Electronic Signature.
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