AD9203-EB(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD9203-EB Datasheet PDF : 19 Pages
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AD9203
Name
1 V Differential
2 V Differential
1 V Single-Ended
2 V Single-Ended
Table I. Modes
Figure Number
Figure 26 with VREF Connected to REFSENSE
Figure 26 with REFSENSE Connected to AGND
Figure 18
Figure 17
Advantages
Differential Modes Yield the Best Dynamic Performance
Differential Modes Yield the Best Dynamic Performance
Video and Applications Requiring Clamping Require
Single-Ended Inputs
Video and Applications Requiring Clamping Require
Single-Ended Inputs
INPUT AND REFERENCE OVERVIEW
Like the voltage applied to the top of the resistor ladder in a
flash A/D converter, the value VREF defines the maximum
input voltage to the A/D core. The minimum input voltage to the
A/D core is automatically defined to be –VREF.
The addition of a differential input structure gives the user an
additional level of flexibility that is not possible with traditional
flash converters. The input stage allows the user to easily config-
ure the inputs for either single-ended operation or differential
operation. The A/D’s input structure allows the dc offset of the
input signal to be varied independently of the input span of the
converter. Specifically, the input to the A/D core is the differ-
ence of the voltages applied at the AINP and AINN input
pins. Therefore, the equation,
VCORE = AINP – AINN
(1)
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage, VCORE, must satisfy the condition,
–VREF ≤ VCORE ≤ VREF
(2)
where VREF is the voltage at the VREF pin.
The actual span (AINP – AINN) of the ADC is ± VREF.
While an infinite combination of AINP and AINN inputs exist
that satisfy Equation 2, an additional limitation is placed on the
inputs by the power supply voltages of the AD9203. The power
supplies bound the valid operating range for AINP and AINN.
The condition,
AVSS – 0.3 V < AINP < AVDD + 0.3 V
(3)
AVSS – 0.3 V < AINN < AVDD + 0.3 V
where AVSS is nominally 0 V and AVDD is nominally +3 V,
defines this requirement. The range of valid inputs for AINP
and AINN is any combination that satisfies both Equations 2
and 3.
INTERNAL REFERENCE CONNECTION
A comparator within the AD9203 will detect the potential of the
VREF pin. If REFSENSE is grounded, the reference amplifier
switch will connect to the resistor divider (see Figure 17). That
will make VREF equal to 1 V. If resistors are placed between
VREF, REFSENSE and ground, the switch will be connected to
the REFSENSE position and the reference amplitude will de-
pend on the external programming resistors (Figure 19). If
REFSENSE is tied to VREF, the switch will also connect to
REFSENSE and the reference voltage will be 0.5 V (Figure 18).
REFTF and REFBF will drive the ADC conversion core and
establish its maximum and minimum span. The range of the
ADC will equal the twice voltage at the reference pin for both
an internal or external reference.
Figure 17 illustrates the input configured with a 1 V reference.
This will set the single-ended input of the AD9203 in the 2 V
span (2 × VREF). This example shows the AINN input is tied
to the 1 V VREF. This will configure the AD9203 to accept a
2 V input centered around 1 V.
2V
0V
AINP
AINN
10F
VREF
0.1F
ADC
CORE
+
0.5V
–
REFTF 2V
0.1F
0.1F
REFBF
1V
10F
0.1F
REFSENSE
LOGIC
AD9203
Figure 17. Internal Reference Set for a 2 V Span
Figure 18 illustrates the input configured with a 0.5 V reference.
This will set the single ended input of the ADC in a 1 V span
(2 × VREF). The AINN input is tied to the 0.5 VREF. This will
configure the AD9203 to accept a 1 V input centered around
0.5 V.
1V
0V
AINP
AINN
10F
VREF
0.1F
ADC
CORE
+
0.5V
–
REFTF 1.75V
0.1F
0.1F
REFBF
1.25V
10F
0.1F
REFSENSE
LOGIC
AD9203
Figure 18. Internal Reference Set for a 1 V Span
–10–
REV. 0
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