P89LPC9301(2009) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC9301
(Rev.:2009)

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash

NXP Semiconductors. 

NXP Semiconductors

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

7.5 Clock output

The P89LPC9301/931A1 supports a user-selectable clock output function on the

P3.0/XTAL2/CLKOUT pin when crystal oscillator is not being used. This condition occurs if

another clock source has been selected (on-chip RC oscillator, watchdog oscillator,

external clock input on XTAL1) and if the RTC and WDT are not using the crystal oscillator

as their clock source. This allows external devices to synchronize to the

P89LPC9301/931A1. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is 1⁄2 that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

7.6 On-chip RC oscillator option

The P89LPC9301/931A1 has a 6-bit TRIM register that can be used to tune the frequency

of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed

value to adjust the oscillator frequency to 7.373 MHz ± 1 % at room temperature.

End-user applications can write to the TRIM register to adjust the on-chip RC oscillator to

other frequencies. When the clock doubler option is enabled (UCFG2.7 = 1), the output

frequency is 14.746 MHz. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can

be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing

highest performance access. This bit can then be set in software if CCLK is running at

8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0

bit (UCFG1.3) are required to hold the device in reset at power-up until VDD has reached

its specified level.

7.7 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to

± 5 % at room temperature. This oscillator can be used to save power when a high clock

frequency is not needed.

7.8 External clock input option

In this configuration, the processor clock is derived from an external source driving the

P3.1/XTAL1 pin. The rate may be from 0 Hz up to 18 MHz. The P3.0/XTAL2/CLKOUT pin

may be used as a standard port pin or a clock output. When using an oscillator frequency

above 12 MHz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the

device in reset at power-up until VDD has reached its specified level.

7.9 Clock sources switch on the fly

P89LPC9301/931A1 can implement clock source switch in any sources of watchdog

oscillator, 7 MHz/14 MHz internal RC oscillator, external clock source (external crystal or

external clock input) during code is running. CLKOK bit in CLKCON register is used to

indicate the clock switch status. CLKOK is cleared when starting clock source switch and

set when completed. Notice that when CLKOK is ‘0’, writing to CLKCON register is not

allowed.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

© NXP B.V. 2009. All rights reserved.

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