P89LPC9301(2009) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC9301
(Rev.:2009)

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash

NXP Semiconductors. 

NXP Semiconductors

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

7.13 Memory organization

The various P89LPC9301/931A1 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and status

registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC9301/931A1 has 4 kB/8 kB of on-chip Code memory.

7.14 Data RAM arrangement

The 256 bytes of on-chip RAM are organized as shown in Table 6.

Table 6.

Type

DATA

IDATA

On-chip data memory usages

Data RAM

Memory that can be addressed directly and indirectly

Memory that can be addressed indirectly

Size (bytes)

128

256

7.15 Interrupts

The P89LPC9301/931A1 uses a four priority level interrupt structure. This allows great

flexibility in controlling the handling of the many interrupt sources. The

P89LPC9301/931A1 supports 13 interrupt sources: external interrupts 0 and 1, timers 0

and 1, serial port TX, serial port RX, combined serial port RX/TX, brownout detect,

watchdog/RTC, I2C-bus, keyboard, comparators 1 and 2, SPI.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in

the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global

disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1 and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt, but

not by another interrupt of the same or lower priority. The highest priority interrupt service

cannot be interrupted by any other interrupt source. If two requests of different priority

levels are pending at the start of an instruction, the request of higher priority level is

serviced.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

© NXP B.V. 2009. All rights reserved.

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