P89LPC9301(2009) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC9301
(Rev.:2009)

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash

NXP Semiconductors. 

NXP Semiconductors

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

7.18.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

7.19 Reset

The P1.5/RST pin can function as either a LOW-active reset input or as a digital input,

P1.5. The Reset Pin Enable (RPE) bit in UCFG1, when set to logic 1, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this pin will function as defined by the RPE bit. Only a power-up reset will

temporarily override the selection defined by RPE bit. Other sources of reset will not

override the RPE bit.

Note: During a power cycle, VDD must fall below VPOR before power is reapplied, in order

to ensure a power-on reset (see Table 10 “Static characteristics”).

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user configured via UCFG1)

• Power-on detect

• Brownout detect

• Watchdog timer

• Software reset

• UART break character detect reset

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These flag bits can be cleared in

software by writing a logic 0 to the corresponding bit. More than one flag bit may be set:

• During a power-on reset, both POF and BOF are set but the other flag bits are

cleared.

• A Watchdog reset is similar to a power-on reset, both POF and BOF are set but the

other flag bits are cleared.

• For any other reset, previously set flag bits that have not been cleared will remain set.

7.19.1 Reset vector

Following reset, the P89LPC9301/931A1 will fetch instructions from either address 0000H

or the Boot address. The Boot address is formed by using the boot vector as the high byte

of the address and the low byte of the address = 00H.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

© NXP B.V. 2009. All rights reserved.

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