P89LPC9301(2009) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC9301
(Rev.:2009)

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash

NXP Semiconductors. 

NXP Semiconductors

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

7.21 RTC/system timer

The P89LPC9301/931A1 has a simple RTC that allows a user to continue running an

accurate timer while the rest of the device is powered down. The RTC can be a wake-up

or an interrupt source. The RTC is a 23-bit down counter comprised of a 7-bit prescaler

and a 16-bit loadable down counter. When it reaches all logic 0s, the counter will be

reloaded again and the RTCF flag will be set. The clock source for this counter can be

either the CPU clock (CCLK) or the XTAL oscillator. Only power-on reset and watchdog

reset will reset the RTC and its associated SFRs to the default state.

The 16-bit loadable counter portion of the RTC is readable by reading the RTCDATL and

RTCDATH registers.

7.22 UART

The P89LPC9301/931A1 has an enhanced UART that is compatible with the conventional

80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The

P89LPC9301/931A1 does include an independent baud rate generator. The baud rate

can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the

independent baud rate generator. In addition to the baud rate generation, enhancements

over the standard 80C51 UART include Framing Error detection, automatic address

recognition, selectable double buffering and several interrupt options. The UART can be

operated in four modes: shift register, 8-bit UART, 9-bit UART, and CPU clock/32 or CPU

clock/16.

7.22.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are

transmitted or received, LSB first. The baud rate is fixed at 1⁄16 of the CPU clock

frequency.

7.22.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0),

8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored

in RB8 in special function register SCON. The baud rate is variable and is determined by

the Timer 1 overflow rate or the baud rate generator (described in Section 7.22.5 “Baud

rate generator and selection”).

7.22.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data

bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is

transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.

Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is

received, the 9th data bit goes into RB8 in special function register SCON, while the stop

bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock

frequency, as determined by the SMOD1 bit in PCON.

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

© NXP B.V. 2009. All rights reserved.

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