P89LPC9301(2009) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
P89LPC9301
(Rev.:2009)
(Rev.:2009)
NXP Semiconductors.
P89LPC9301 Datasheet PDF : 65 Pages
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NXP Semiconductors
P89LPC9301/931A1
8-bit microcontroller with accelerated two-clock 80C51 core
7.22.9 Transmit interrupts with double buffering enabled (modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the TI interrupt is generated
when the double buffer is ready to receive new data.
7.22.10 The 9th bit (bit 8) in double buffering (modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as long
as TB8 is updated some time before that bit is shifted out. TB8 must not be changed until
the bit is shifted out, as indicated by the TI interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8 will
be double-buffered together with SBUF data.
7.23 I2C-bus serial interface
The I2C-bus uses two wires (SDA and SCL) to transfer information between devices
connected to the bus, and it has the following features:
• Bidirectional data transfer between masters and slaves
• Multi master bus (no central master)
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
• The I2C-bus may be used for test and diagnostic purposes.
A typical I2C-bus configuration is shown in Figure 7. The P89LPC9301/931A1 device
provides a byte-oriented I2C-bus interface that supports data transfers up to 400 kHz.
I2C-bus
RP
RP
P1.3/SDA P1.2/SCL
P89LPC9301/931A1
OTHER DEVICE
WITH I2C-BUS
INTERFACE
Fig 7. I2C-bus configuration
SDA
SCL
OTHER DEVICE
WITH I2C-BUS
INTERFACE
002aae455
P89LPC9301_931A1_1
Preliminary data sheet
Rev. 01 — 9 April 2009
© NXP B.V. 2009. All rights reserved.
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