P89LPC9301(2009) View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC9301
(Rev.:2009)

8-bit microcontroller with accelerated two-clock 80C51 core 4 kB/8 kB 3 V byte-erasable flash

NXP Semiconductors. 

NXP Semiconductors

P89LPC9301/931A1

8-bit microcontroller with accelerated two-clock 80C51 core

If requests of the same priority level are pending at the start of an instruction, an internal

polling sequence determines which request is serviced. This is called the arbitration

ranking. Note that the arbitration ranking is only used to resolve pending requests of the

same priority level.

7.15.1 External interrupt inputs

The P89LPC9301/931A1 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard 80C51

microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by

setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle

and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an

interrupt request.

If an external interrupt is enabled when the P89LPC9301/931A1 is put into Power-down or

Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer

to Section 7.18 “Power reduction modes” for details.

RTCF

ERTC

(RTCCON.1)

WDOVF

IE0

EX0

IE1

EX1

BOIF

EBO

KBIF

EKBI

EWDRT

CMF2

CMF1

EC

EA (IE0.7)

TF0

ET0

TF1

ET1

TI and RI/RI

ES/ESR

TI

EST

SI

EI2C

SPIF

ESPI

Fig 5. Interrupt sources, interrupt enables, and power-down wake-up sources

wake-up

(if in power-down)

interrupt

to CPU

002aae453

P89LPC9301_931A1_1

Preliminary data sheet

Rev. 01 — 9 April 2009

© NXP B.V. 2009. All rights reserved.

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