P89LPC932A1FDH View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC932A1FDH

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

7.19.7 Alternating output mode

In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating

pairs for bridge drive control. In this mode the output of these PWM channels are

alternately gated on every counter cycle.

TOR2

COMPARE VALUE A (or C)

COMPARE VALUE B (or D)

TIMER VALUE

0

PWM OUTPUT (OCA or OCC)

Fig 11. Alternate output mode

PWM OUTPUT (OCB or OCD)

002aaa895

7.19.8 PLL operation

The PWM module features a PLL that can be used to generate a CCUCLK frequency

between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic

PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or

higher. The PLL is fed an input signal from 0.5 MHz to 1 MHz and generates an output

signal of 32 times the input frequency. This signal is used to clock the timer. The user will

have to set a divider that scales PCLK by a factor from 1 to 16. This divider is found in the

SFR register TCR21. The PLL frequency can be expressed as shown in Equation 1.

PLL frequency = (--P-N---C---+-L---K-1----)

(1)

Where: N is the value of PLLDV[3:0].

Since N ranges from 0 to 15, the CCLK frequency can be in the range of PCLK to PCLK⁄16.

P89LPC932A1_3

Product data sheet

Rev. 03 — 12 March 2007

© NXP B.V. 2007. All rights reserved.

29 of 64

Share Link: