P89LPC932A1FDH View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC932A1FDH

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

7.20.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data

bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is

transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of logic 0 or logic 1.

Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is

received, the 9th data bit goes into RB8 in Special Function Register SCON, while the stop

bit is not saved. The baud rate is programmable to either 1⁄16 or 1⁄32 of the CPU clock

frequency, as determined by the SMOD1 bit in PCON.

7.20.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8

data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). In fact, Mode 3 is

the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable

and is determined by the Timer 1 overflow rate or the Baud Rate Generator (described in

Section 7.20.5 “Baud rate generator and selection”).

7.20.5 Baud rate generator and selection

The P89LPC932A1 enhanced UART has an independent Baud Rate Generator. The baud

rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0 SFRs

which together form a 16-bit baud rate divisor value that works in a similar manner as

Timer 1 but is much more accurate. If the baud rate generator is used, Timer 1 can be

used for other timing functions.

The UART can use either Timer 1 or the baud rate generator output (see Figure 13). Note

that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is cleared. The

independent Baud Rate Generator uses OSCCLK.

timer 1 overflow

(PCLK-based)

baud rate generator

(CCLK-based)

SMOD1 = 1

÷2

SMOD1 = 0

Fig 13. Baud rate sources for UART (Modes 1, 3)

SBRGS = 0

baud rate modes 1 and 3

SBRGS = 1

002aaa897

7.20.6 Framing error

Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6)

is logic 1, framing errors can be made available in SCON.7 respectively. If SMOD0 is

logic 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6) are set up

when SMOD0 is logic 0.

7.20.7 Break detect

Break detect is reported in the status register (SSTAT). A break is detected when

11 consecutive bits are sensed LOW. The break detect can be used to reset the device

and force the device into ISP mode.

P89LPC932A1_3

Product data sheet

Rev. 03 — 12 March 2007

© NXP B.V. 2007. All rights reserved.

31 of 64

Share Link: