P89LPC932A1FDH View Datasheet(PDF) - NXP Semiconductors.

Part Name

Description

Manufacturer

P89LPC932A1FDH

8-bit microcontroller with accelerated two-clock 80C51 core 8 kB 3 V byte-erasable flash with 512-byte data EEPROM

NXP Semiconductors. 

NXP Semiconductors

P89LPC932A1

8-bit microcontroller with accelerated two-clock 80C51 core

Table 10. Dynamic characteristics (18 MHz)

VDD = 3.0 V to 3.6 V unless otherwise specified.

Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2]

Symbol Parameter

Conditions

Variable clock

Min

Max

fosc = 18 MHz Unit

Min Max

fOSC(RC)

fOSC(WD)

internal RC oscillator frequency

internal watchdog oscillator

frequency

7.189

280

7.557

480

7.189 7.557 MHz

280 480 kHz

fosc

oscillator frequency

Tcy(CLK) clock cycle time

fCLKLP

low power select clock frequency

Glitch filter

see Figure 23

0

18

-

- MHz

55

-

-

- ns

0

8

-

- MHz

tgr

glitch rejection

P1.5/RST pin

any pin except

P1.5/RST

-

50

-

50 ns

-

15

-

15 ns

tsa

signal acceptance

P1.5/RST pin

125

-

125

- ns

any pin except

50

-

50

- ns

P1.5/RST

External clock

tCHCX

clock HIGH time

tCLCX

clock LOW time

tCLCH

clock rise time

tCHCL

clock fall time

Shift register (UART mode 0)

see Figure 23

see Figure 23

see Figure 23

see Figure 23

22

Tcy(CLK) − tCLCX 22

22

Tcy(CLK) − tCHCX 22

-

5

-

-

5

-

- ns

- ns

5 ns

5 ns

tXLXL

serial port clock cycle time

see Figure 22

16Tcy(CLK)

-

tQVXH

output data set-up to clock rising see Figure 22

13Tcy(CLK)

-

edge time

888

- ns

722

- ns

tXHQX

output data hold after clock rising see Figure 22

edge time

-

Tcy(CLK) + 20

-

75 ns

tXHDX

input data hold after clock rising see Figure 22

edge time

-

0

-

0 ns

tXHDV

input data valid to clock rising

see Figure 22

150

-

150

- ns

edge time

SPI interface

fSPI

SPI operating frequency

slave

0

CCLK⁄6

0

3.0 MHz

master

-

CCLK⁄4

-

4.5 MHz

TSPICYC

SPI cycle time

slave

see Figure 24,

25, 26, 27

6⁄CCLK

-

333

- ns

master

4⁄CCLK

-

222

- ns

tSPILEAD

SPI enable lead time

2.0 MHz (slave)

see Figure 26, 27

250

-

250

- ns

tSPILAG

SPI enable lag time

2.0 MHz (slave)

see Figure 26, 27

250

-

250

- ns

P89LPC932A1_3

Product data sheet

Rev. 03 — 12 March 2007

© NXP B.V. 2007. All rights reserved.

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