STE100P(2000) View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

STE100P
(Rev.:2000)

10/100 FAST ETHERNET 3.3V TRANSCEIVER

STMicroelectronics 

STE100P

7.10 Reset Operation

There are two ways to reset the STE100P. First, for hardware reset, the STE100P can be reset via RESET pin

(pin 29). The active low Reset input signal is required at least 1 ms to ensure proper reset operation. Second,

for software reset, when bit 15 of register PR0 is set to 1, the STE100P will reset entire circuits and registers to

their default values, then clear the bit 15 of PR0 to 0, and set the RIP output pin 63 to logic 1. Both hardware

and software reset operations initialize all registers to their default values. This process includes re-evaluation

of all hardware-configurable registers. Logic levels on several I/O pins are detected during hardware reset pe-

riod to determine the initial functionality of STE100P. Some of these pins are used as outputs after the reset

operation. Care must be taken to ensure that the configuration setup will not interfere with normal operation.

Dedicated configuration pins can be tied to the Vcc or ground directly. Configuration pins multiplexed with LED

outputs should be weakly pulled up or weakly pulled down through resistors as shown in the following circuits.

I/O PIN

Vcc

10kΩ

10kΩ

I/O PIN

Logic Level 1

Logic Level 0

7.11 Preamble Suppression

Preamble suppression mode in the STEPHY1 is indicated by a one in bit six of the PR1 Register. If it is deter-

mined that all PHY devices in the system support preamble suppression, then a preamble is not necessary for

each management transaction. The first transaction following power-up/hardware reset requires 32 bits of pre-

amble. The full 32 bit preamble is not required for each additional transaction. The STEPHY1 will respond to

management accesses without preamble, but a minimum of one idle bit between management transactions is

required as specified in IEEE 802.3u.

7.12 Remote Fault

The remote fault function indicates to a link partner that a fault condition has occurred by using the Remote Fault

bit, which is encoded in bit 13 of the Link Code Word. A local device indicates to its link partner that it has found

a fault by setting the Remote Fault bit in the Auto-Negotiation register to logic one and renegotiating with the

link partner. The Remote Fault bit remains at logic one until successful negotiation with the Link Code Word

occurs. The bit will then return to 0. When the message is sent that the Remote Fault bit is set to logic one, the

device will set the Remote Fault bit in the MII to logic one if the management function is present.

7.13 Transmit Isolation

STA/STE

Ethernet

ttp

STEPHY1

4/5

tpn

RxD

4/5

TxD

MII

TX(100MHz)/TP(10MHz)

18/29

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