STE100P(2000) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STE100P Datasheet PDF : 29 Pages
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STE100P
Table 1. Pin Description
Pin No. Name
Type
37-33 LED/PAD
I/O
Pins
37
LED10/
I/O
PAD[4]
36
LEDTR/
PAD[3]
35
LEDL
I/O
/PAD[2]
34
LEDC
I/O
/
PAD[1]
33
LEDS
I/O
/
PAD[0]
31
CFG0
I
32
CFG1
I
Pin No.
29
Name
RESET
Type
I
63
RIP
O
Description
Pins 33-37 are multifunction pins used as LED outputs and PHY Address sensing
inputs for multiple PHY applications. PHY address sensing is achieved by
strapping a pull-up/pull-down resistor (typically 10 kΩ) to this pin as required.
The active state of each LED output driver is dependent on the logic level
sampled by the corresponding PHY address input upon power-up/reset. If a
given PAD input is resistively pulled low, the corresponding LED output will be
configured as an active high driver. Conversely, if a given PAD input is resistively
pulled high then the corresponding LED output will be configured as an active low
driver.
These outputs are standard CMOS voltage drivers and not open-drain.
LED display for 10Ms/s link status. This pin will be driven on continually when
10Mb/s network operating speed is detected.
The pull-up/pull-down status of this pin is latched into the PR20 bit 7 during
power up/reset.
LED display for Tx/Rx Activity status. This pin will be driven on with 10 Hz
blinking frequency when either effective receiving or transmitting is detected.
The status of this pin is latched into the PR20 bit 6 during power up/reset.
LED display for Link Status. This pin will be driven on continually when a good
Link test is detected.
The status of this pin is latched into the PR20 bit 5 during power up/reset.
LED display for Full Duplex or Collision status. This pin will be driven on
continually when a full duplex configuration is detected. This pin will be driven on
with 20 Hz blinking frequency when a collision status is detected in the half
duplex configuration.
The status of this pin is latched into the PR20 bit 4 during power up/reset.
LED display for 100Ms/s link status. This pin will be driven on continually when
100Mb/s network operating speed is detected.
The status of this pin is latched into the PR20 bit 3 during power up/reset.
Configuration Control 0.
When A/N is enabled, CFG0 determines operating mode advertisement
capabilities in combination with CFG1 when MF0/ PR0:12 =1. (See Table 2)
When A/N is disabled, CFG1 disables MLT3 and directly affects PR19:0
When CFG0 is Low, MLT3 encoder/decoder is enabled and PR19:1 =0.
When CFG0 is High, MLT3 encoder/decoder is bypassed and PR19:1 = 1.
Configuration Control 1.
When A/N is enabled, CFG1 determines operating mode advertisement
capabilities in combination with CFG1 when MF0/ PR0:12 =1. (See Table 2)
When A/N is disabled, CFG1 enables Loopback mode and directly affects PR0
bit 14.
When CFG1 is Low, Loopback mode is disabled and PR0:14 = 0.
When CFG1 is High, Loopback mode is enabled and PR0:14 = 1.
Description
Reset (Active-Low). This input must be held low for a minimum of 1 ms to reset
the STE100P. During Power-up, the STE100P will be reset regardless of the
state of this pin, and this reset will not be complete until after >1ms.
Reset In Progress. This output is used to indicate when the device has
completed power-up/reset and the registers and functions can be accessed.
When RIP is High, power-up/reset has been successful and the device can be
used normally
When RIP is Low, device reset is not complete.
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