STE100P(2000) View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
STE100P Datasheet PDF : 29 Pages
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STE100P
6.1 Register List
Table 3. Register List
Address
Reg. Index
0
PR0
1
PR1
2
PR2
3
PR3
4
PR4
5
PR5
6
PR6
17
PR17
18
PR18
19
PR19
20
PR20
Name
XCR
XSR
PID1
PID2
ANA
ANLPA
ANE
XCIIS
XIE
100CTR
XMC
Register Descriptions
XCVR Control Register
XCVR Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
XCVR Configuration Information and Interrupt Status Register
XCVR Interrupt Enable Register
100BASE-TX PHY Control/Status Register
XCVR Mode Control Register
6.2 Register Descriptions
Table 4. Register Descriptions
Bit #
Name
Descriptions
Default Val RW Type
PR0- XCR, XCVR Control Register. The default values on power-up/reset are as listed below.
15
XRST Reset control.
0
R/W
1: Device will be reset. This bit will be cleared by STE100P
itself after the reset is completed.
14
XLBEN Loop-back mode select.
1: Loop-back mode is selected.
0
R/W
13
SPSEL Network Speed select. This bit’s selection will be ignored if
1
R/W
Auto-Negotiation is enabled(bit 12 of PR0 = 1).
1:100Mbps is selected.
0:10Mbps is selected.
12
ANEN Auto-Negotiation ability control.
1: Auto-Negotiation function is enabled.
0: Auto-Negotiation is disabled.
1
R/W
11
PDEN Power-down mode control.
0
R/W
1: Power-down mode is selected. Setting this bit puts the
STE100P into power-down mode. During the power-down
mode, TXP/TXN and all LED outputs are 3-stated, and the
MII interface is isolated.
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