SAF-C505C-2RM View Datasheet(PDF) - Infineon Technologies
Part Name
Description
Manufacturer
SAF-C505C-2RM Datasheet PDF : 88 Pages
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C505 / C505C
C505A / C505CA
Timer / Counter 0 and 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in table 6 :
Table 6
Timer/Counter 0 and 1 Operating Modes
Mode Description
0
8-bit timer/counter with a
divide-by-32 prescaler
1
16-bit timer/counter
2
8-bit timer/counter with
8-bit autoreload
3
Timer/counter 0 used as one
8-bit timer/counter and one
8-bit timer
Timer 1 stops
TMOD
M1 M0
00
01
10
11
Input Clock
internal
external (max)
fOSC/6x32
fOSC/12x32
fOSC/6
fOSC/12
In the “timer” function (C/T = ‘0’) the register is incremented every machine cycle. Therefore the
count rate is fOSC/6.
In the “counter” function the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a
falling edge the max. count rate is fOSC/12. External inputs INT0 and INT1 (P3.2, P3.3) can be
programmed to function as a gate to facilitate pulse width measurements. Figure 10 illustrates the
input clock logic.
OSC
P3.4/T0
P3.5/T1
Gate
=1
(TMOD)
P3.2/INT0
P3.3/INT1
÷6
C/T = 0
C/T = 1
TR0
TR1
&
<_ 1
f OSC/6
Timer 0/1
Input Clock
Control
MCS03117
Figure 10
Timer/Counter 0 and 1 Input Clock Logic
Data Sheet
28
08.00
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