SAF-C505C-2RM View Datasheet(PDF) - Infineon Technologies
Part Name
Description
Manufacturer
SAF-C505C-2RM Datasheet PDF : 88 Pages
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C505 / C505C
C505A / C505CA
Compare Mode 1
If compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the
new value will not appear at the output pin until the next compare match occurs. Thus, it can be
choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the
actual pin-level) or should keep its old value at the time when the timer value matches the stored
compare value.
In compare mode 1 (see figure 13) the port circuit consists of two separate latches. One latch
(which acts as a "shadow latch") can be written under software control, but its value will only be
transferred to the port latch (and thus to the port pin) when a compare match occurs.
Port Circuit
Compare Register
Circuit
Compare Reg.
16 Bit
Comparator
16 Bit
Timer Register
Timer Circuit
Compare
Match
Internal
Bus
Write to
Latch
Figure 13
Compare Function in Compare Mode 1
Read Latch
VDD
D
Q
D
Q
Port
Shadow
Port
Pin
Latch
Latch
CLK
CLK
Q
Read Pin
MCS02662
Timer 2 Capture Modes
Each of the compare/capture registers CC1 to CC3 and the CRC register can be used to latch the
current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for this
function.
In mode 0, the external event causing a capture is :
– for CC registers 1 to 3: a positive transition at pins CC1 to CC3 of port 1
– for the CRC register: a positive or negative transition at the corresponding pin, depending
on the status of the bit I3FR in SFR T2CON.
In mode 1 a capture occurs in response to a write instruction to the low order byte of a capture
register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The timer 2
contents will be latched into the appropriate capture register in the cycle following the write
instruction. In this mode no interrupt request will be generated.
Data Sheet
32
08.00
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