SAF-C505C-2RM View Datasheet(PDF) - Infineon Technologies
Part Name
Description
Manufacturer
SAF-C505C-2RM Datasheet PDF : 88 Pages
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C505 / C505C
C505A / C505CA
10-Bit A/D Converter (C505A and C505CA only)
The C505A/C505CA includes a high performance / high speed 10-bit A/D-Converter (ADC) with 8
analog input channels. It operates with a successive approximation technique and uses self
calibration mechanisms for reduction and compensation of offset and linearity errors. The A/D
converter provides the following features:
– 8 multiplexed input channels (port 1), which can also be used as digital inputs/outputs
– 10-bit resolution
– Single or continuous conversion mode
– Internal start-of-conversion trigger capability
– Interrupt request generation after each conversion
– Using successive approximation conversion technique via a capacitor array
– Built-in hidden calibration of offset and linearity errors
The 10-bit ADC uses two clock signals for operation : the conversion clock fADC (=1/tADC) and the
input clock fIN (=1/tIN). fADC is derived from the C505 system clock fOSC which is applied at the
XTAL pins. The input clock fIN is equal to fOSC The conversion fADC clock is limited to a maximum
frequency of 2 MHz. Therefore, the ADC clock prescaler must be programmed to a value which
assures that the conversion clock does not exceed 2 MHz. The prescaler ratio is selected by the
bits ADCL1 and ADCL0 of SFR ADCON1.
ADCL1
ADCL0
f OSC
32
16 MUX
8
4
Conversion Clock f ADC
A/D
Converter
Clock Prescaler
Input Clock f IN
Condition: f ADC max < 2 MHz
f IN = f OSC
=
1
CLP
MCU System Clock fIN
Rate (fOSC)
[MHz]
2 MHz
2
6 MHz
6
8 MHz
8
12 MHz
12
16 MHz
16
20 MHz
20
Prescaler
Ratio
÷4
÷4
÷4
÷8
÷8
÷ 16
fADC
[MHz]
0.5
1.5
2
1.5
2
1.25
Figure 19
10-Bit A/D Converter Clock Selection
Data Sheet
40
MCS03635
ADCL1 ADCL0
0
0
0
0
0
0
0
1
0
1
1
0
08.00
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