SAF-C505C-2RM View Datasheet(PDF) - Infineon Technologies
Part Name
Description
Manufacturer
SAF-C505C-2RM Datasheet PDF : 88 Pages
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C505 / C505C
C505A / C505CA
Fail Save Mechanisms
The C505 offers enhanced fail safe mechanisms, which allow an automatic recovery from software
upset or hardware failure :
– a programmable watchdog timer (WDT), with variable time-out period from 192 µs up to
approx. 393.2 ms at 16 MHz (314.5 ms at 20 MHz).
– an oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state in case the on-chip oscillator fails; it also provides the clock for
a fast internal reset after power-on.
The watchdog timer in the C505 is a 15-bit timer, which is incremented by a count rate of fOSC/12
upto fOSC/192. The system clock of the C505 is divided by two prescalers, a divide-by-two and a
divide-by-16 prescaler. For programming of the watchdog timer overflow rate, the upper 7 bits of the
watchdog timer can be written. Figure 24 shows the block diagram of the watchdog timer unit.
f OSC / 6
2
16
0
7
WDTL
OWDS WDTS
WDT Reset - Request
IP0 (A9 H)
14
8
WDTH
WDTPSEL
External HW Reset
WDT
SWDT
Control Logic
76
0
WDTREL (86H )
IEN0 (A8H )
IEN1 (B8H )
MCB03306
Figure 24
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT in SFR IEN1) but it cannot be stopped
during active mode of the device. If the software fails to refresh the running watchdog timer an
internal reset will be initiated on watchdog timer overflow. For refreshing of the watchdog timer the
content of the SFR WDTREL is transfered to the upper 7-bit of the watchdog timer. The refresh
sequence consists of two consequtive instructions which set the bits WDT and SWDT each. The
reset cause (external reset or reset caused by the watchdog) can be examined by software (flag
WDTS). It must be noted, however, that the watchdog timer is halted during the idle mode and
power down mode of the processor.
Data Sheet
46
08.00
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