PIC16LCR72-10I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LCR72-10I/SS

8-Bit CMOS microcontroller with A,D converter

Microchip Technology 

PIC16C72 Series

FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) (PIC16C72)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN

bit7

CKP

SSPM3 SSPM2 SSPM1 SSPM0

bit0

R = Readable bit

W = Writable bit

U = Unimplemented bit,

read as ‘0’

- n =Value at POR reset

bit 7: WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word

(must be cleared in software)

0 = No collision

bit 6: SSPOV: Receive Overflow Detect bit

In SPI mode

1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of over-

flow, the data in SSPSR register is lost. Overflow can only occur in slave mode. The user must read the

SSPBUF, even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is

not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.

0 = No overflow

In I2C mode

1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t

care" in transmit mode. SSPOV must be cleared in software in either mode.

0 = No overflow

bit 5: SSPEN: Synchronous Serial Port Enable bit

In SPI mode

1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins

0 = Disables serial port and configures these pins as I/O port pins

In I2C mode

1 = Enables the serial port and configures the SDA and SCL pins as serial port pins

0 = Disables serial port and configures these pins as I/O port pins

In both modes, when enabled, these pins must be properly configured as input or output.

bit 4: CKP: Clock Polarity Select bit

In SPI mode

1 = Idle state for clock is a high level. Transmit happens on falling edge, receive on rising edge.

0 = Idle state for clock is a low level. Transmit happens on rising edge, receive on falling edge.

In I2C mode

SCK release control

1 = Enable clock

0 = Holds clock low (clock stretch) (Used to ensure data setup time)

bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI master operation, clock = Fosc/4

0001 = SPI master operation, clock = Fosc/16

0010 = SPI master operation, clock = Fosc/64

0011 = SPI master operation, clock = TMR2 output/2

0100 = SPI slave mode, clock = SCK pin. SS pin control enabled.

0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.

0110 = I2C slave mode, 7-bit address

0111 = I2C slave mode, 10-bit address

1011 = I2C firmware controlled master operation (slave idle)

1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled

1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled

© 1998 Microchip Technology Inc.

Preliminary

DS39016A-page 41

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