PIC16LCR72-10I/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16LCR72-10I/SS

8-Bit CMOS microcontroller with A,D converter

Microchip Technology 

PIC16C72 Series

8.2.1 OPERATION OF SSP MODULE IN SPI

MODE - PIC16C72

• SCK (Slave mode) must have TRISC<3> set

• SS must have TRISA<5> set (if implemented)

A block diagram of the SSP Module in SPI Mode is

shown in Figure 8-3.

The SPI mode allows 8-bits of data to be synchro-

nously transmitted and received simultaneously. To

accomplish communication, typically three pins are

used:

• Serial Data Out (SDO) RC5/SDO

• Serial Data In (SDI) RC4/SDI/SDA

• Serial Clock (SCK)

RC3/SCK/SCL

Additionally a fourth pin may be used when in a slave

mode of operation:

• Slave Select (SS)

RA5/SS/AN4

When initializing the SPI, several options need to be

specified. This is done by programming the appropriate

control bits in the SSPCON register (SSPCON<5:0>).

These control bits allow the following to be specified:

• Master Operation (SCK is the clock output)

• Slave Mode (SCK is the clock input)

• Clock Polarity (Output/Input data on the Rising/

Falling edge of SCK)

• Clock Rate (master operation only)

• Slave Select Mode (Slave mode only)

To enable the serial port, SSP enable bit SSPEN

(SSPCON<5>) must be set. To reset or reconfigure SPI

mode, clear enable bit SSPEN, re-initialize SSPCON

register, and then set enable bit SSPEN. This config-

ures the SDI, SDO, SCK, and SS pins as serial port

pins. For the pins to behave as the serial port function,

they must have their data direction bits (in the TRIS reg-

ister) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (master operation) must have TRISC<3>

cleared

FIGURE 8-3: SSP BLOCK DIAGRAM

(SPI MODE)

Read

Internal

data bus

Write

SSPBUF reg

RC4/SDI/SDA

RC5/SDO

SSPSR reg

bit0

shift

clock

RA5/SS/AN4

SS Control

Enable

Edge

Select

2

Clock Select

RC3/SCK/

SCL

SSPM3:SSPM0

4

Edge

Select

TMR2 output

2

Prescaler TCY

4, 16, 64

TRISC<3>

TABLE 8-1 REGISTERS ASSOCIATED WITH SPI OPERATION

Address Name

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2

Bit 1

Bit 0

Value on:

POR,

BOR

Value on

all other

resets

0Bh,8Bh

0Ch

8Ch

87h

INTCON

PIR1

PIE1

TRISC

GIE

PEIE T0IE INTE

(1)

ADIF

(1)

(1)

(1)

ADIE

(1)

(1)

PORTC Data Direction Register

RBIE T0IF INTF RBIF 0000 000x 0000 000u

SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

1111 1111 1111 1111

13h

SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

14h

SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000

85h

TRISA

—

— PORTA Data Direction Register

--11 1111 --11 1111

94h

SSP-

STAT

—

—

D/A

P

S

R/W

UA

BF --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode.

Note 1: These bits are unimplemented, read as '0'.

DS39016A-page 42

Preliminary

© 1998 Microchip Technology Inc.

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