PIC16LC924-08/CL View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC16LC924-08/CL Datasheet PDF : 189 Pages
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PIC16C9XX
FIGURE 17-13:I2C BUS DATA TIMING
SCL
SDA
In
103
90
91
100
101
106
107
109
109
SDA
Out
Refer to Figure 17-2 for load conditions.
102
92
110
TABLE 17-11:I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max Units
Conditions
100*
THIGH Clock high time
100 kHz mode
4.0
—
µs Device must operate at a mini-
mum of 1.5 MHz
SSP Module
1.5TCY
—
101*
TLOW Clock low time
100 kHz mode
4.7
—
µs Device must operate at a mini-
mum of 1.5 MHz
SSP Module
1.5TCY
—
102*
TR SDA and SCL rise
time
100 kHz mode
—
1000 ns
103*
TF SDA and SCL fall time 100 kHz mode
—
300
ns
90*
TSU:STA START condition
setup time
100 kHz mode
4.7
—
µs Only relevant for repeated
START condition
91*
THD:STA START condition hold 100 kHz mode
time
4.0
—
µs After this period the first clock
pulse is generated
106*
THD:DAT Data input hold time 100 kHz mode
0
—
ns
107*
TSU:DAT Data input setup time 100 kHz mode
250
—
ns
92*
TSU:STO STOP condition setup 100 kHz mode
time
4.7
—
µs
109*
TAA Output valid from
clock
100 kHz mode
—
3500 ns Note 1
110*
TBUF Bus free time
100 kHz mode
4.7
—
µs Time the bus must be free
before a new transmission can
start
D102*
Cb Bus capacitive loading
—
400 pF
*
Characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCL to avoid unintended generation of START or STOP conditions.
© 1997 Microchip Technology Inc.
DS30444E - page 157
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