PIC16C923T-08I/SP View Datasheet(PDF) - Microchip Technology
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PIC16C923T-08I/SP Datasheet PDF : 189 Pages
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PIC16C9XX
12.1 A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-4. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS) imped-
ance varies over the device voltage (VDD),
(Figure 12-4). The source impedance affects the offset
voltage at the analog input (due to pin leakage current).
The maximum recommended impedance for ana-
log sources is 10 kΩ. After the analog input channel is
selected (changed) this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation calculates
the acquisition time to within 1/2 LSb error (512 steps
for the A/D). The 1/2 LSb error is the maximum error
allowed for the A/D to meet its specified accuracy.
EQUATION 12-1: A/D MINIMUM CHARGING
TIME
VHOLD = (VREF - (VREF/512)) • (1 - e(-Tc/CHOLD(RIC + RSS + RS)))
Given: VHOLD = (VREF/512), for 1/2 LSb resolution
The above equation reduces to:
TC = -(51.2 pF)(1 kΩ - RSS + RS) ln(1/511)
Example 12-1 shows the calculation of the minimum
required acquisition time (TACQ). This calculation is
based on the following system assumptions.
CHOLD = 51.2 pF
Rs = 10 kΩ
1/2 LSb error
VDD = 5V → Rss = 7 kΩ
Temp (system max.) = 50°C
VHOLD = 0 @ t = 0
FIGURE 12-4: ANALOG INPUT MODEL
VDD
Rs RAx
VT = 0.6V
VA
CPIN
5 pF
VT = 0.6V
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
Note 2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
Note 3: The maximum recommended impedance
for analog sources is 10 kΩ. This is
required to meet the pin leakage specifi-
cation.
Note 4: After a conversion has completed, a
2.0 TAD delay must complete before
acquisition can begin again. During this
time the holding capacitor is not con-
nected to the selected A/D input channel.
EXAMPLE 12-1: CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
TACQ = Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
TACQ = 5 µs + Tc + [(Temp - 25°C)(0.05 µs/°C)]
TC = -CHOLD (RIC + RSS + RS) ln(1/511)
-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)
-51.2 pF (18 kΩ) ln(0.0020)
-0.921 µs (-6.2364)
5.747 µs
TACQ = 5 µs + 5.747 µs + [(50°C - 25°C)(0.05 µs/°C)]
10.747 µs + 1.25 µs
11.997 µs
RIC ≤ 1k
Sampling
Switch
SS RSS
I leakage
± 500 nA
CHOLD
= DAC capacitance
= 51.2 pF
VSS
Legend CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
SS
CHOLD
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
6V
5V
VDD 4V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
( kΩ )
DS30444E - page 82
© 1997 Microchip Technology Inc.
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