PIC16C9XX
FIGURE 13-2: LCD MODULE BLOCK DIAGRAM
Data Bus
LCD
RAM
32 x 4
128
to
32
MUX
SEG<31:0>
TO I/O PADS
Timing Control
LCDCON
LCDPS
LCDSE
COM3:COM0
TO I/O PADS
Internal RC osc
T1CKI
Fosc/4
Clock
Source
Select
and
Divide
FIGURE 13-3: LCDPS REGISTER (ADDRESS 10Eh)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
—
—
—
—
LP3 LP2 LP1 LP0
bit7
bit0
bit 7-4: Unimplemented, read as '0'
bit 3-0: LP3:LP0: Frame Clock Prescale Selection bits
R =Readable bit
W =Writable bit
U =Unimplemented bit, Read as ‘0’
-n =Value at POR reset
LMUX1:LMUX0
00
01
10
11
Multiplex
Static
1/2
1/3
1/4
Frame Frequency =
Clock source / (128 * (LP3:LP0 + 1))
Clock source / (128 * (LP3:LP0 + 1))
Clock source / (96 * (LP3:LP0 + 1))
Clock source / (128 * (LP3:LP0 + 1))
DS30444E - page 90
© 1997 Microchip Technology Inc.