NXP Semiconductors
PCA85176
Universal LCD driver for low multiplex rates
12. Application information
12.1 Cascaded operation
Large display configurations of up to 16 PCA85176 can be recognized on the same
I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable
I2C-bus slave address (SA0).
Table 18.
Cluster
1
2
Addressing cascaded PCA85176
Bit SA0
Pin A2
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
Pin A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Pin A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Device
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
When cascaded PCA85176 are synchronized, they can share the backplane signals from
one of the devices in the cascade. Such an arrangement is cost-effective in large LCD
applications since the backplane outputs of only one device need to be through-plated to
the backplane electrodes of the display. The other PCA85176 of the cascade contribute
additional segment outputs, but their backplane outputs are left open-circuit
(see Figure 23).
PCA85176_1
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 14 April 2010
© NXP B.V. 2010. All rights reserved.
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