PCA9541AD View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
Manufacturer
PCA9541AD Datasheet PDF : 41 Pages
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NXP Semiconductors
PCA9541A
2-to-1 I2C-bus master selector with interrupt logic and reset
[4] Cb = total capacitance of one bus line in pF.
[5] Measurements taken with 1 kΩ pull-up resistor and 50 pF load.
[6] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
[7] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus.
SDA
tBUF
SCL
tr
tLOW
tHD;STA
P
S
tHD;DAT
tf
tHIGH
tSU;DAT
Fig 23. Definition of timing on the I2C-bus
tHD;STA
tSP
tSU;STA
Sr
tSU;STO
P
002aaa986
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
SCL
SDA
tSU;STA
tBUF
tLOW tHIGH
1/fSCL
tr
tf
bit 0 acknowledge
(R/W)
(A)
STOP
condition
(P)
tHD;STA
Rise and fall times, refer to VIL and VIH.
Fig 24. I2C-bus timing diagram
tSU;DAT tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
002aab175
PCA9541A_3
Product data sheet
Rev. 03 — 16 July 2009
© NXP B.V. 2009. All rights reserved.
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