ST52T441F3M6 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST52T441F3M6

8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG

STMicroelectronics 

ST52T400/T440/E440/T441

2.4 Arithmetic Logic Unit

ST52x400/440/441 supplies 46 instructions that

perform computations and control the device.

Computational time required for each instruction

consists of one clock pulse for each Cycle plus 2

clock pulses for the decoding phase. Total compu-

tation time for each instruction is reported in Table

2.5

The ALU of the ST52x400/440/441 can perform

multiplication (MULT) and division (DIV). Multipli-

cation is performed by using 8 bit operands stor-

ing the result in 2 registers (16 bit values).

Division is performed between a 16 bit dividend

and an 8 bit divider, the result and the remainder

are stored in two 8-bit registers.

WARNING: If the LSB of the multiplication result

is 0, the Zero flag is set although the result is not

0.

2.4.1 Addressing Modes.

ST52x400/440/441 instructions allow the following

addressing modes:

Inherent: this instruction type does not require an

operand because the opcode specifies all the

information necessary to carry out the instruction.

Examples: NOP, RET.

Immediate: these instructions have an operand as

a source immediate value. Examples: LDRC,

PGSET.

Direct: the operands of these instructions are

specified with the direct addresses. The operands

can refer, according to the opcode, to addresses

belonging to the different addressing spaces.

Example: SUB, LDRE.

Indirect: data addresses that are required are

found in the locations specified as operands. Both

source and/or destination operands can be

addressed indirectly. The operands can refer,

(according to the opcode) to addresses belonging

to different addressing spaces. Examples: LDRE

(reg1),(reg2).

2.4.2 Instruction Types.

ST FIVE supplies the following instruction types:

s Load Instructions

s Arithmetic and Logic Instructions

s Jump Instructions

s Interrupt Management Instructions

s Control Instructions

The instructions are listed in Table 2.5, Table 2.6

and Table 2.7.

Table 2.5 Arithmetic & Logic Instruction Set

Load Instructions

Mnemonic

Instruction

Bytes

Cycles

Z

S

C

LDCE

LDCE confx,memx

3

17

-

-

-

LDCR

LDRC confx,regx

3

14

-

-

-

LDFR

LDFR fuzzyx,regx

3

14

-

-

-

LDPE

LDPE outx,memx

3

17

-

-

-

LDPE

LDPE outx,(regx)

3

17

-

-

-

LDPR

LDPR outx,regx

3

14

-

-

-

LDRC

LDRC regx,const

3

14

-

-

-

LDRE

LDRE regx,memx

3

16

-

-

-

LDRE

LDRE (regx),(regy)

3

18

-

-

-

LDRI

LDRI regx,inpx

3

15

-

-

-

LDRR

LDRR regx, regy

3

16

-

-

-

PGSET

PGSET const

2

9

-

-

-

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