ST52T441 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST52T441

8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG

STMicroelectronics 

ST52T400/T440/E440/T441

Figure 4.5 Interrupt Configuration Registers 17 and 18

Interrupts Priority

REG_CONF18

REG_CONF17

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

INT 1

INT 2

INT 3

INT 4

INT 5

Not Used

4.5 Interrupt Priority

Seven priority levels are available: level 6 has the

lowest priority, level 0 has the highest priority.

Level 6 is associated to the Main Program, levels

5 to 1 are programmable by means of the priority

registers called REG_CONF17 and

REG_CONF18; whereas the higher level is

related to the External Interrupt (INT_EXT).

PWM/Timer, TRIAC/PWM and Analog Block are

identified by a three-bit Peripheral Code (see

Table 4.2); in order to set the i-th priority level the

user must write the peripheral label i in the related

INTi priority level.

For instance:

LDRC 10,193 (loads the value 193=’11000001’

in the RAM Register 10)

LDRC 11,168 (loads the value 168=’10101000’

in the RAM Register 11)

LDCR 17,10 (REG_CONF17= ‘11000001’)

LDCR 18,11 (REG_CONF18= ‘10101000’)

thus defining the following priority levels:

s Level 1: INT_PWM/TIMER (PWM/TIMER Code:

001)

s Level 2: INT_ADC (ADC Code: 000)

s Level 3: INT_TRIAC/PWM_R (TRIAC/PWM

Code: 011)

s Level 4: INT_TRIAC/Ph (TRIAC/Ph Code: 100)

s Level 5: INT_TRIAC/PWM_F (TRIAC/PWM_F

Code: 010)

Table 4.3 Conf. Registers 17-18 Description

Bit

0, 1, 2

3, 4, 5

6, 7, 8

9, 10, 11

12, 13,

Name

INT1

INT2

INT4

INT5

INT6

Value

Peripheral

Peripheral

Peripheral

Peripheral

Peripheral

Level

High

MediumHigh

MediumLow

Low

Very Low

REMARK: The Interrupt priority must be set at the

beginning of the main program, because at the

RESET REG_CONF1=’00000000’, this condition

could generate wrong operations. Further,

changing the priority levels must be avoided in

interrupt service routines.

When a source provides an Interrupt request, and

the request processing is also enabled, the CU

changes the normal sequential flow of a program

by transferring program control to a selected ser-

vice routine.

When an interrupt occurs the CU executes a

JUMP instruction to the address loaded in the

related location of the Interrupt Vector and the

flags are saved.

When the execution returns to the original pro-

40/94

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