ST52T441 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST52T441

8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG

STMicroelectronics 

cient for optimum results (recommended capaci-

tance values range is 10-1000 nF). The optimum

linearity in conversion can be obtained if the volt-

age level on the selected input channel does not

exceed a maximum of 3 V. In the second case, if

an external ramp generator is used, the

REG_CONF16[(1)] bit must be set to “1”.

The 16 bit Timer, directly triggered by the output of

the Analog Comparator, allows the measurement

of the conversion time that is proportional to the

analog value.

The device clock is divided by an internal 12 bit

Prescaler to generate the appropriate Timer clock

that allows the desired resolution to be obtained

with a reasonable conversion time.

When an appropriate value of the capacitor is

selected, the conversion should be complete

before the full count is reached. A timer overflow

flag is set once the Timer reaches its maximum

count value.

Generally, the maximum conversion time of the A/

D converter depends on the capacitor chosen and

the charge current. The maximum conversion time

can be calculated by using the following formula:

ConversionTime(ms)

=

C-----(--n----F----)---×-----F----u----l--l--S---c----a---l--e---(---V----)

Ch argeCurrent(uA)

C is the capacitance in nF, FullScale is the maxi-

mum voltage recommended for the input signal,

which is 3 V, and ChargeCurrent is the configured

value of the current for charging the capacitor.

To obtain the desired resolution, the prescaler

value has to be set in accordance to the following

formula:

P

=

-C----(--n----F----)---×-----C-----K----M------(--M------H----z---)----×----F----u----l--l--S----c---a---l--e----(--V----)----×----1---0---3-

Ch arg e Curr ent( uA) × 2RESOLUTION

–

1

CMK indicates the Master Clock frequency and

Resolution is the number of bits that should con-

tain the converted values. Recommended values

for the resolution are in the range between 8-14

bits.

After the Capacitor is charged, it is discharged in a

number of clock cycles equivalent to (P+1) x 410.

When the external ramp generator is used, a ris-

ing ramp or a falling ramp may be chosen. In this

case, the timer counter should be specified to be

either an up counter (REG_CONF3[(3)]=0) or a

down counter (REG_CONF3[(3)]=1).

By using a rising ramp the Analog Comparator

ST52T400/T440/E440/T441

must be configured to trigger the signal when it

crosses the compared value from low to high

(REG_CONF3[(2)]=0); vice versa, using a falling

ramp, the polarity should be set to trigger the sig-

nal in crossing from high to low

(REG_CONF3[(2)]=1).

When the Capacitor is used, it generates a rising

ramp. For this reason the polarity must be config-

ured to trigger the crossing from low to

high(REG_CONF3[(2)]=0).

In order to synchronize the external ramp signal

and the timer, the ACSTRT and ACSYNC pin

have to be used. The input pin ACSTRT is used to

start the timer when the external ramp is started

(ACSTRT=1). The ACSYNC output pin provides

the handshake signal, which (when ACSYNC=1)

furnishes information indicating that the timer is

ready to receive the start signal.

If the input signal is too high, the counter may

overflow. When this happens, bit 0 of the Input

Register 13 AC_STATUS (Table 2.1) is set to 1

and an interrupt is generated at the end of count.

If the counter is configured in down counting, the

bit is set when the counter goes in underflow.

7.3.1 Operating Modes.

In order to avoid the errors introduced by the A/D

components drift, a periodic conversion of the

internal reference signals can be performed in

order to calibrate the converted values. Two differ-

ent internal voltage references are available:

1) Bandgap voltage, this reference voltage can

also be used externally for analog signal condi-

tioning.

2) GNDA.

Setting the REG_CONF1[(0)] to “1” the peripheral

converts the reference signal after converting

each analog signal. In order to choose the refer-

ence, REG_CONF3[(1)] should be configured.

To ensure secure and stable measurements, sev-

eral measurements on the same channel and

mediating the obtained results are recommended.

The conversion of each single channel may be

repeated up to three times by configuring the

REG_CONF1[(7:6)].

The analog multiplexer allows the user to work in

four different modes:

– Single Channel Single Conversion

– Single Channel Multiple Conversions

– Multiple Channels Single Conversion

– Multiple Channels Multiple Conversions

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