ST52T441 View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST52T441

8-BIT INTELLIGENT CONTROLLER UNIT (ICU) Timer/PWM, Analog Comparator, Triac/PWM Timer, WDG

STMicroelectronics 

ST52T400/T440/E440/T441

8.2 Register Description

WDT Timeout period can be set by setting the first

4 bits of REG_CONF2: this allows 16 different val-

ues of WDT Clock pulse number to be defined.

The WDT CLK is derived from the Master Clock

divided by 500. Timeout is then obtained by multi-

plying the WDT CLK period for the number of

pulses defined in configuration register

REG_CONF2. Table 8.4 illustrates the pulse

length for typical values of Master Clock.

Table 8.3 illustrates the timeout WDT values when

Master Clock is 5 MHz.

Table 8.2 WDT REG_CONF2

Bit Name Value Timeout Values (WDT

CLK pulses)

0000

0

0001

0010

0011

0100

1

0101

0110

D(3:0)

0111

1000

2

1001

1010

1011

1100

3

1101

1110

1111

4-7

NC

x

1

625

1250

1875

2500

3125

3750

4375

5000

5625

6250

6875

7500

8125

8750

9375

Not Used

Table 8.3 Timeout Values with CLKM=5 MHz

Bit

Name

Value

0000

0

0001

0010

0011

0100

1

0101

0110

D(3:0)

0111

1000

2

1001

1010

1011

1100

3

1101

1110

1111

4-7

NC

x

Reset Configuration ‘0000’

Timeout Values

0.1

62.5

125

187.5

250

312.5

375

437.5

500

562.5

625

687.5

750

812.5

875

937.5

Not Used

Table 8.4 Typical WDT CLK PERIOD

MASTER CLK

(MHz)

4

5

8

10

20

WDT CLK

(KHz)

8

10

16

20

40

WDT CLK

PERIOD (ms)

0.125

0.1

0.0625

0.05

0.025

Reset Configuration ‘0000’

55/94

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