PIC16CR620A-04E/SS View Datasheet(PDF) - Microchip Technology

Part Name

Description

Manufacturer

PIC16CR620A-04E/SS

EPROM-Based 8-Bit CMOS Microcontrollers

Microchip Technology 

PIC16C62X

9.5.1 RB0/INT INTERRUPT

External interrupt on RB0/INT pin is edge triggered,

either rising if INTEDG bit (OPTION<6>) is set, or fall-

ing, if INTEDG bit is clear. When a valid edge appears

on the RB0/INT pin, the INTF bit (INTCON<1>) is set.

This interrupt can be disabled by clearing the INTE

control bit (INTCON<4>). The INTF bit must be cleared

in software in the interrupt service routine before re-

enabling this interrupt. The RB0/INT interrupt can

wake-up the processor from SLEEP, if the INTE bit was

set prior to going into SLEEP. The status of the GIE bit

decides whether or not the processor branches to the

interrupt vector following wake-up. See Section 9.8 for

details on SLEEP and Figure 9-18 for timing of wake-

up from SLEEP through RB0/INT interrupt.

FIGURE 9-16:

INT PIN INTERRUPT TIMING

9.5.2 TMR0 INTERRUPT

An overflow (FFh → 00h) in the TMR0 register will

set the T0IF (INTCON<2>) bit. The interrupt can

be enabled/disabled by setting/clearing T0IE

(INTCON<5>) bit. For operation of the Timer0 module,

see Section 6.0.

9.5.3 PORTB INTERRUPT

An input change on PORTB <7:4> sets the RBIF

(INTCON<0>) bit. The interrupt can be enabled/dis-

abled by setting/clearing the RBIE (INTCON<4>) bit.

For operation of PORTB (Section 5.2).

Note:

If a change on the I/O pin should occur

when the read operation is being executed

(start of the Q2 cycle), then the RBIF

interrupt flag may not get set.

9.5.4 COMPARATOR INTERRUPT

See Section 7.6 for complete description of comparator

interrupts.

OSC1

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CLKOUT 3

4

INT pin

1

INTF flag

5

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

PC

PC

Instruction

fetched

Inst (PC)

Instruction

executed

Inst (PC-1)

1

Interrupt Latency 2

PC+1

Inst (PC+1)

Inst (PC)

PC+1

—

Dummy Cycle

0004h

Inst (0004h)

Dummy Cycle

0005h

Inst (0005h)

Inst (0004h)

Note 1: INTF flag is sampled here (every Q1).

2: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.

3: CLKOUT is available only in RC Oscillator mode.

4: For minimum width of INT pulse, refer to AC specs.

5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

DS30235J-page 56

 2003 Microchip Technology Inc.

Share Link: