ST72521AR7TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72521AR7TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

CONTROLLER AREA NETWORK (Cont’d)

– ERROR. The error management as described in

the CAN protocol is completely handled by hard-

ware using 2 error counters which get increment-

ed or decremented according to the error

condition. Both of them may be read by the appli-

Figure 70. CAN Error State Diagram

cation to determine the stability of the network.

Moreover, as one of the node status bits (EPSV

or BOFF of the CSR register) changes, an inter-

rupt is generated if the SCIE bit is set in the ICR

Register. Refer to Figure 70.

When TECR or RECR > 127, the EPSV bit gets set

ERROR ACTIVE

ERROR PASSIVE

When 128 * 11 recessive bits occur:

- the BOFF bit gets cleared

- the TECR register gets cleared

- the RECR register gets cleared

When TECR and RECR < 128,

the EPSV bit gets cleared

When TECR > 255 the BOFF bit gets set

and the EPSV bit gets cleared

BUS OFF

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