ST72521AR7TC View Datasheet(PDF) - STMicroelectronics

Part Name

Description

Manufacturer

ST72521AR7TC

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

CONTROLLER AREA NETWORK (Cont’d)

CONTROL/STATUS REGISTER (CSR)

Read/Write

Reset Value: 00h

7

0

0 BOFF EPSV SRTE NRTX FSYN WKPS RUN

B−itR6e=adBOOnFlFy Bus-Off State

Set by hardware to indicate that the node is in bus-

off state, i.e. the Transmit Error Counter exceeds

255.

Reset by hardware to indicate that the node is in-

volved in bus activities.

B−itR5e=adEPOSnVly Error Passive State

Set by hardware to indicate that the node is error

passive.

Reset by hardware to indicate that the node is either

error active (BOFF = 0) or bus-off.

Bit 4

able

−=

SRTE Simultaneous

Read/Set/Clear

Receive/Transmit

En-

Set by software to enable simultaneous transmis-

sion and reception of a message passing the ac-

ceptance filtering. Allows to check the integrity of

the communication path.

Reset by software to discard all messages trans-

mitted by the node. Allows remote and data frames

to share the same identifier.

−BitR3e=adN/RSeTtX/CNleoaRr etransmission

Set by software to disable the retransmission of un-

successful messages.

Cleared by software to enable retransmission of

messages until success is met.

B−itR2e=adF/SSYeNt/CFleaasrt Synchronization

Set by software to enable a fast resynchronization

when leaving standby mode, i.e. wait for only 11 re-

cessive bits in a row.

Cleared by software to enable the standard resyn-

chronization when leaving standby mode, i.e. wait

for 128 sequences of 11 recessive bits.

B−itR1e=adW/SKePt/SClWeaarke-up Pulse

Set by software to generate a dominant pulse when

leaving standby mode.

Cleared by software for no dominant wake-up

pulse.

B−itR0e=adR/USeNt/CCAleNarEnable

Set by software to leave standby mode after 128 se-

quences of 11 recessive bits or just 11 recessive

bits if FSYN is set.

Cleared by software to request a switch to the

standby or low-power mode as soon as any on-go-

ing transfer is complete. Read-back as 1 in the

meantime to enable proper signalling of the standby

state. The CPU clock may therefore be safely

switched OFF whenever RUN is read as 0.

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