INTERRUPTS (Cont’d)
Figure 17. Interrupt Processing Flowchart
FROM RESET
N
I BIT SET?
Y
FETCH NEXT INSTRUCTION
ST7LITE0x, ST7LITESx
N
INTERRUPT
PENDING?
Y
N
EXECUTE INSTRUCTION
IRET?
Y
STACK PC, X, A, CC
SET I BIT
LOAD PC FROM INTERRUPT VECTOR
RESTORE PC, X, A, CC FROM STACK
THIS CLEARS I BIT BY DEFAULT
Table 6. Interrupt Mapping
N°
Source
Block
Description
RESET Reset
TRAP
Software Interrupt
0
Not used
1
ei0
External Interrupt 0
2
ei1
External Interrupt 1
3
ei2
External Interrupt 2
4
ei3
External Interrupt 3
5
Not used
6
Not used
7
SI
AVD interrupt
8
AT TIMER Output Compare Interrupt
AT TIMER
9
AT TIMER Overflow Interrupt
10
LITE TIMER Input Capture Interrupt
LITE TIMER
11
LITE TIMER RTC Interrupt
12
SPI
SPI Peripheral Interrupts
13
Not used
Register
Label
Priority
Order
Highest
Priority
Exit
from
HALT
yes
no
N/A
yes
SICSR
no
PWM0CSR
no
ATCSR
yes
LTCSR
no
LTCSR
yes
SPICSR Lowest yes
Priority
Address
Vector
FFFEh-FFFFh
FFFCh-FFFDh
FFFAh-FFFBh
FFF8h-FFF9h
FFF6h-FFF7h
FFF4h-FFF5h
FFF2h-FFF3h
FFF0h-FFF1h
FFEEh-FFEFh
FFECh-FFEDh
FFEAh-FFEBh
FFE8h-FFE9h
FFE6h-FFE7h
FFE4h-FFE5h
FFE2h-FFE3h
FFE0h-FFE1h
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