ST7LITE0x, ST7LITESx
9 POWER SAVING MODES
9.1 INTRODUCTION
To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 21): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.
After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency (fOSC).
From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the oscillator
status.
Figure 21. Power Saving Mode Transitions
High
RUN
SLOW
9.2 SLOW MODE
This mode has two targets:
– To reduce power consumption by decreasing the
internal clock in the device,
– To adapt the internal clock frequency (fCPU) to
the available supply voltage.
SLOW mode is controlled by the SMS bit in the
MCCSR register which enables or disables Slow
mode.
In this mode, the oscillator frequency is divided by
32. The CPU and peripherals are clocked at this
lower frequency.
Notes:
SLOW-WAIT mode is activated when entering
WAIT mode while the device is already in SLOW
mode.
SLOW mode has no effect on the Lite Timer which
is already clocked at FOSC/32.
Figure 22. SLOW Mode Clock Transition
fCPU
fOSC/32
fOSC
WAIT
fOSC
SLOW WAIT
SMS
ACTIVE HALT
HALT
Low
POWER CONSUMPTION
NORMAL RUN MODE
REQUEST
38/125
1