ST6285BQ1 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
Manufacturer
ST6285BQ1 Datasheet PDF : 78 Pages
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ST62T85B/E85B
TIMER (Cont’d)
4.2.3 Application Notes
Bit 4 = DOUT: Data Output
TMZ is set when the counter reaches zero; howev- Data sent to the timer output when TMZ is set high
er, it may also be set by writing 00h in the TCR (output mode only). Input mode selection (input
register or by setting bit 7 of the TSCR register. mode only).
The TMZ bit must be cleared by user software Bit 3 = PSI: Prescaler Initialize Bit
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine. After reset, the 8-bit counter register is
loaded with 0FFh, while the 7-bit prescaler is load-
ed with 07Fh, and the TSCR register is cleared.
This means that the Timer is stopped (PSI=“0”)
Used to initialize the prescaler and inhibit its count-
ing. When PSI=“0” the prescaler is set to 7Fh and
the counter is inhibited. When PSI=“1” the prescal-
er is enabled to count downwards. As long as
PSI=“0” both counter and prescaler are not run-
ning.
and the timer interrupt is disabled.
Bit 2, 1, 0 = PS2, PS1, PS0: Prescaler Mux. Se-
If the Timer is programmed in output mode, the lect. These bits select the division ratio of the pres-
DOUT bit is transferred to the TIMER pin when caler register.
TMZ is set to one (by software or due to counter
decrement). When TMZ is high, the latch is trans-
parent and DOUT is copied to the timer pin. When
) TMZ goes low, DOUT is latched.
t(s A write to the TCR register will predominate over
c the 8-bit counter decrement to 00h function, i.e. if a
u write and a TCR register decrement to 00h occur
d simultaneously, the write will take precedence,
ro and the TMZ bit is not set until the 8-bit counter
reaches 00h again. The values of the TCR and the
P PSC registers can be read accurately at any time.
te 4.2.4 Timer Registers
le Timer Status Control Register (TSCR)
so Address: 0D4h — Read/Write
b 7
0
- O TMZ ETI TOUT DOUT PSI PS2 PS1 PS0
t(s) Bit 7 = TMZ: Timer Zero bit
c A low-to-high transition indicates that the timer
u count register has decrement to zero. This bit must
d be cleared by user software before starting a new
ro count.
P Bit 6 = ETI: Enable Timer Interrupt
te When set, enables the timer interrupt request. If
le ETI=0 the timer interrupt is disabled. If ETI=1 and
TMZ=1 an interrupt request is generated.
so Bit 5 = TOUT: Timers Output Control
bWhen low, this bit selects the input mode for the
OTIMER pin. When high the output mode is select-
Table 15. Prescaler Division Factors
PS2
PS1
PS0 Divided by
0
0
0
1
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Timer Counter Register TCR
Address: 0D3h — Read/Write
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7-0 = D7-D0: Counter Bits.
Prescaler Register PSC
Address: 0D2h — Read/Write
7
0
D7 D6 D5 D4 D3 D2 D1 D0
Bit 7 = D7: Always read as “0”.
ed.
Bit 6-0 = D6-D0: Prescaler Bits.
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