ST6285BQ1 View Datasheet(PDF) - STMicroelectronics
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ST6285BQ1 Datasheet PDF : 78 Pages
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ST62T85B/E85B
4.3 AUTO-RELOAD TIMER
The Auto-Reload Timer (AR Timer) on-chip pe- ning or not. Initialization of the counter, by either
ripheral consists of an 8-bit timer/counter with method, will also clear the ARPSC register, where-
compare and capture/reload capabilities and of a upon counting will start from a known value.
7-bit prescaler with a clock multiplexer, enabling
the clock input to be selected as fINT, fINT/3. A
Mode Control Register, ARMC, two Status Control
Registers, ARSC0 and ARSC1, allow the Auto-
Reload Timer to be used in 2 modes:
4.3.2 Timer Auto-reload Operating Modes
The free running 8-bit counter is fed by the pres-
caler’s output, and is incremented on every rising
edge of the clock signal.
– Auto-reload mode,
– Output compare,
When a counter overflow occurs, the counter is
automatically reloaded with the contents of the Re-
load/Capture Register, ARCC. The period be-
The AR Timer can be used to wake the MCU from tween two overflows is then controlled by the pres-
WAIT mode with an internal clock. A Load register caler setting and by the auto-reload value present
allows the program to read and write the counter in the Reload/Capture register, ARRC.
on the fly.
On overflow, the OVF flag of the ARSC0 register is
4.3.1 AR Timer Description
The AR COUNTER is an 8-bit up-counter incre-
) mented on the input clock’s rising edge. The coun-
t(s ter is loaded from the ReLoad/Capture Register,
c ARRC, for auto-reload operations, as well as for
u initialization. Direct access to the AR counter is not
d possible; however, by reading or writing the ARLR
ro load register, it is possible to read or write the
counter’s contents on the fly.
P The AR Timer’s input clock can be either the inter-
te nal clock (from the Oscillator Divider), or the inter-
le nal clock divided by 3. Selection between these
o clock sources is effected by suitably programming
s bits CC0-CC1 of the ARSC1 register. The output
b of the AR Multiplexer feeds the 7-bit programma-
O ble AR Prescaler, ARPSC, which selects one of
- the 8 available taps of the prescaler, as defined by
) PSC0-PSC2 in the AR Mode Control Register.
t(s Thus the division factor of the prescaler can be set
to 2n (where n = 0, 1,..7).
uc The clock input to the AR counter is enabled by the
d TEN (Timer Enable) bit in the ARMC register.
ro When TEN is reset, the AR counter is stopped and
the prescaler and counter contents are frozen.
P When TEN is set, the AR counter runs at the rate
te of the selected clock source. The counter is
cleared on system reset.
ole The AR counter may also be initialized by writing
s to the ARLR load register, which also causes an
bimmediate copy of the value to be placed in the AR
Ocounter, regardless of whether the counter is run-
set and an overflow interrupt request is generated
if the overflow interrupt enable bit, OVIE, in the
Mode Control Register (ARMC), is set. The OVF
flag must be reset by the user software.
When the counter reaches the compare value, the
CPF flag of the ARSC0 register is set and a com-
pare interrupt request is generated, if the Compare
Interrupt enable bit, CPIE, in the Mode Control
Register (ARMC), is set.
Notes. The compare value loaded in the Compare
Register, ARCP, must be in the range from (AR-
RC) to 255.
The ARTC counter is initialized by writing to the
ARRC register and by then setting the TCLD (Tim-
er Load) and the TEN (Timer Clock Enable) bits in
the Mode Control register, ARMC.
Enabling and selection of the clock source is con-
trolled by the CC0, CC1, SL0 and SL1 bits in the
Status Control Register, ARSC1. The prescaler di-
vision ratio is selected by the PS0, PS1 and PS2
bits in the ARSC1 register.
The clock frequency should not be modified while
the counter is counting, since the counter may be
set to an unpredictable value. For instance, the
multiplexer setting should not be modified while
the counter is counting.
Loading of the counter by any means (by auto-re-
load, through ARLR, ARRC or by the Core) resets
the prescaler at the same time.
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