PIC10F220IP(2006) View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC10F220IP Datasheet PDF : 78 Pages
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PIC10F220/222
FIGURE 6-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
PC
(Program
Counter)
Instruction
Fetch
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
PC
PC + 1
PC + 2
PC + 3
PC + 4
PC + 5
PC + 6
MOVWF TMR0 MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Timer0
T0
Instruction
Executed
T0 + 1
NT0
NT0 + 1
Write TMR0 Read TMR0 Read TMR0
executed
reads NT0 reads NT0
Read TMR0 Read TMR0 Read TMR0
reads NT0 reads NT0 + 1 reads NT0 + 2
TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0
Address
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
01h
TMR0
Timer0 – 8-Bit Real-Time Clock/Counter
N/A
N/A
Legend:
OPTION
GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0
TRISGPIO(1)
—
—
—
— I/O Control Register
Shaded cells not used by Timer0, – = unimplemented, x = unknown, u = unchanged.
Note 1: The TRIS of the T0CKI pin is overridden when T0CS = 1
Value on
Power-On
Reset
xxxx xxxx
1111 1111
---- 1111
Value on
All Other
Resets
uuuu uuuu
1111 1111
---- 1111
6.1 Using Timer0 With An External
Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock require-
ment is due to internal phase clock (TOSC) synchroniza-
tion. Also, there is a delay in the actual incrementing of
Timer0 after synchronization.
6.1.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks (Figure 6-4).
Therefore, it is necessary for T0CKI to be high for at
least 2TOSC (and a small RC delay of 2Tt0H) and low
for at least 2TOSC (and a small RC delay of 2Tt0H).
Refer to the electrical specification of the desired
device.
When a prescaler is used, the external clock input is
divided by the asynchronous ripple counter-type
prescaler, so that the prescaler output is symmetrical.
For the external clock to meet the sampling require-
ment, the ripple counter must be taken into account.
Therefore, it is necessary for T0CKI to have a period of
at least 4TOSC (and a small RC delay of 4Tt0H) divided
by the prescaler value. The only requirement on T0CKI
high and low time is that they do not violate the
minimum pulse width requirement of Tt0H. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
DS41270B-page 26
Preliminary
© 2006 Microchip Technology Inc.
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