PIC10F220-I(2006) View Datasheet(PDF) - Microchip Technology
Part Name
Description
Manufacturer
PIC10F220-I Datasheet PDF : 78 Pages
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PIC10F220/222
FIGURE 8-6:
WATCHDOG TIMER BLOCK DIAGRAM
From Timer0 Clock Source
(Figure 6-5)
Watchdog
Timer
WDT Enable
Configuration
Bit
0
M
1U
X
PSA
Postscaler
8-to-1 MUX
3
PS<2:0>
0
1
MUX
To Timer0 (Figure 6-4)
PSA
WDT Time-out
Note 1: T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.
TABLE 8-4: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-On
Reset
Value on
All Other
Resets
N/A
OPTION GPWU GPPU T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u = unchanged.
8.7 Time-out Sequence, Power-down
and Wake-up from Sleep Status
Bits (TO/PD/GPWUF/CWUF)
The TO, PD and GPWUF bits in the STATUS register
can be tested to determine if a Reset condition has
been caused by a Power-up condition, a MCLR,
Watchdog Timer (WDT) Reset or wake-up on pin
change.
TABLE 8-5: TO/PD/GPWUF STATUS AFTER RESET
GPWUF
TO
PD
Reset Caused By
0
0
0
WDT wake-up from Sleep
0
0
u
WDT time-out (not from Sleep)
0
1
0
MCLR wake-up from Sleep
0
1
1
Power-up
0
u
u
MCLR not during Sleep
1
1
0
Wake-up from Sleep on pin change
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.
Note 1: The TO, PD and GPWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR
input does not change the TO, PD or GPWUF Status bits.
© 2006 Microchip Technology Inc.
Preliminary
DS41270B-page 39
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