PIC10F220/222
FIGURE 10-3:
RESET, WATCHDOG TIMER AND DEVICE RESET TIMER TIMING
VDD
MCLR
Internal
POR
32
DRT
Timeout(2)
Internal
Reset
Watchdog
Timer
Reset
I/O pin(1)
30
32
32
31
34
34
Note 1: I/O pins must be taken out of High-impedance mode by enabling the output drivers in software.
2: Runs on POR Reset only.
TABLE 10-4: RESET, WATCHDOG TIMER AND DEVICE RESET TIMER
AC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature -40°C ≤ TA ≤ +85°C (industrial)
-40°C ≤ TA ≤ +125°C (extended)
Param
No.
Sym
Characteristic
Min Typ(1) Max Units
Conditions
30
TMCL MCLR Pulse Width (low)
2000* —
—
ns VDD = 5.0V
31
TWDT Watchdog Timer Time-out Period 9* 18* 30* ms VDD = 5.0V (Industrial)
(no prescaler)
9* 18* 40* ms VDD = 5.0V (Extended)
32
TDRT Device Reset Timer Period
0.5* 1.125* 2*
0.5* 1.125* 2.5*
ms VDD = 5.0V (Industrial)
ms VDD = 5.0V (Extended)
34
TIOZ I/O High-impedance from MCLR
—
— 2000* ns
low
* These parameters are characterized but not tested.
Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design
guidance only and are not tested.
FIGURE 10-4:
TIMER0 CLOCK TIMINGS
T0CKI
40
41
42
DS41270B-page 58
Preliminary
© 2006 Microchip Technology Inc.